// DATA is open-collector 8bit data bus
	// P1 serves as address selector for UART's registers, /ADS is always low

	// set divisor = 48, that is 9600 baud with 7.372.800 Hz cystall
	// seems this section does not cause any problems
	UART_CS = 0;
	P1 = (P1 & ~UART_ADR_MASK) | UART_LCR;
	DATA = 0x80; //prepare for DLSB setup
	nWR = 0;
	nWR = 1;
	P1 = (P1 & ~UART_ADR_MASK) | UART_RBR_THR_DLL;
	DATA = 48; 
	nWR = 0;
	nWR = 1;
	DATA = 3; // 1 stop bit, no parity, reset DLAB to 0
	P1 = (P1 & ~UART_ADR_MASK) | UART_LCR;
	nWR = 0;
	nWR = 1;

	// write a byte to Tx, this causes problems
	DATA = 'A';
	P1 = (P1 & ~UART_ADR_MASK) | UART_RBR_THR_DLL;
	nWR = 0;
	nWR = 1;
	for (temp2 = 0; temp2 < 1; temp2++) // there are problems if these ...
		for (temp1 = 0; temp1 < 100; temp1++); // ... do-nothing loops are not included


	DATA = 0xFF; // disconnect bus from ground allowing UART assert a value to it
	P1 = (P1 & ~UART_ADR_MASK) | UART_LSR; // select address of status register
	nRD = 0;	// put contents of addressed register on the bus
	for(;;)	{			/*start of endless loop*/
		send_byte(DATA); // def = 60
		delay_msec(1000);	/*wait about a second*/
	}