module counter
    (input wire clk,
     input wire rst_l,
     input wire clear,
     output reg [31:0] q);

    always @(posedge clk or negedge rst_l) begin : CountMe

	if (~rst_l) begin
	    q <= 32'd0;
	end else begin
	    if (clear)
		q <= 32'd0;
	    else
		q <= q + 32'd1;
	end // else: !if(~rst_l)
    end // block: CountMe
endmodule // counter