config() function is below.

init_COM() is in the original post

void config (void)
{
	int n = 0;

	WDTCN = 0x07;	// Watchdog Timer Control Register
   WDTCN = 0xDE;   // Disable WDT
   WDTCN = 0xAD;
	
   SFRPAGE = 0x0F;
	XBR0 = 0x04;	// XBAR0: Initial Reset Value
	XBR1 = 0x00;	// XBAR1: Initial Reset Value
	XBR2 = 0x44;	// XBAR2: Initial Reset Value added on 11 July 2004 for Com2

	SFRPAGE = 0x0F;
	P0MDOUT = 0x05; // Output configuration for P0 
	P1MDOUT = 0x00; // Output configuration for P1 
	P2MDOUT = 0x00; // Output configuration for P2 
	P3MDOUT = 0x00; // Output configuration for P3 
	P4MDOUT = 0x00; // Output configuration for P4
	P5MDOUT = 0x00; // Output configuration for P5
	P6MDOUT = 0x00; // Output configuration for P6
	P7MDOUT = 0x00; // Output configuration for P7

   P1MDIN = 0xFF;  // Input configuration for P1

// Oscillator Configuration	

    SFRPAGE = 0x00;
    FLSCL = 0x10;   // FLASH Memory Control

    SFRPAGE = 0x0F;
	 OSCXCN = 0x00;	// EXTERNAL Oscillator Control Register
/*	
    for (n = 0; n < 1000; n++) ;            // wait for osc to start
    while ( (OSCXCN & 0x80) == 0 );        // wait for xtal to stabilize
*/

	 OSCICN = 0xC3;	// 83 ALSO SAME Internal Oscillator Control Register

	 PLL0CN = 0;

    PLL0DIV = 0x01; // PLL pre-divide Register 
    PLL0FLT = 0x31; // PLL Filter Register
    PLL0MUL = 0x02; // PLL Clock scaler Register
    PLL0CN = 0x01;  // PLL Control Register

    for(n = 0; n < 500; n++);               // wait at least 5us
    PLL0CN |= 0x02;                         // enable PLL
    while ( (PLL0CN & 0x10) == 0 );        // wait for PLL to lock

// select PLL as clock source

    CLKSEL = 0x02;  // Oscillator Clock Selector
	
//----------------------------------------------------------------
// UART0 Configuration
//----------------------------------------------------------------

    SFRPAGE = 0x00;
    SADEN0 = 0x00;      // Serial 0 Slave Address Enable
    SADDR0 = 0x00;      // Serial 0 Slave Address Register

//	 SMOD0 = 1 disable  baud rate devide / 2
//  Timer3 Generates Baud Rate 

    SSTA0 = 0x1A;       // UART0 Status and Clock Selection Register

// UART0 Mode 1 8bit auto variable baud rate

    SCON0 = 0x50;       // Serial Port Control Register
    SCON0 &= 0xFC; 	   //clear interrupt pending flags

    PCON = 0x00;        // Power Control Register

// UART1 Configuration

    SFRPAGE = 0x01;     // Baud Rate same as Uart0 38400
    SCON1 = 0x10;       // Serial Port 1 Control Register   
    SCON1 &= 0xFC; 	   // clear interrupt pending flags
                        // tested on 11 July 2004.OK

// Timers Configuration

    SFRPAGE = 0x00;
	 // Timer 1 uses SYSCLK as time base
	 // timer0/1 prescales = SYSCLK / 4
    CKCON = 0x01;   // Clock Control Register

// timer 1 generates UART1 baud rate
// TIMER 1 USES CLK PRESCALER. TIME BASE IS SYSCLK / 4

    TL0 = 0x00;     // Timer 0 Low Byte
    TH0 = 0xee;     // Timer 0 High Byte 
    TL1 = 0x00;     // Timer 1 Low Byte
    TH1 = 0x61;     // Timer 1 High Byte 
    TMOD = 0x22;    // Timer Mode Register 8bit auto reload
    TCON = 0x50;    // Timer Control Register 

// Timer 3 for UART0 BAUD GENERATOR		
// Time Base is SYSCLK @ 49MHZ
// Baud Rate 38765  = FFB1
// Baud Rate 117788 = FFE6

    SFRPAGE = 0x01;
    TMR3CF = 0x08;  // 0 Timer 3 Configuration
    RCAP3L = 0xB1;  // Timer 3 Reload Register Low Byte
    RCAP3H = 0xFF;  // Timer 3 Reload Register High Byte
    TMR3H = 0x00;   // Timer 3 High Byte
    TMR3L = 0x00;   // Timer 3 Low Byte
    TMR3CN = 0x04;  // Timer 3 Control Register

   SFRPAGE = 0x00;
	RSTSRC = 0x00;	// Reset Source Register 

// Interrupt Configuration
//----------------------------------------------------------------

//    IE = 0xA1;          //Interrupt Enable
    IP = 0x00;          //Interrupt Priority
    EIE1 = 0x00;        //Extended Interrupt Enable 1
    EIE2 = 0x00;        //Extended Interrupt Enable 2
    EIP1 = 0x00;        //Extended Interrupt Priority 1
    EIP2 = 0x00;        //Extended Interrupt Priority 2

	 SFRPGCN = 0x00;

}   //End of config

i hope this would be sifficient.

many thanks

haribabu