; This program provides an example of how to configure the ADC
; An internal 24500000Hz crystal is used as the system clock source.;
; EQUATES


$include (c8051f310.inc) ; Include register definition file.

LED EQU P3.3 ; LED on target board ('1' is LED ON)

INTCLK EQU 24500000/8 ; Intenal oscillator frequency

; VARIABLES

; ADC data variables
ADC_READING EQU 29H; holding register for ADC READING (16-bit)
; 2 Bytes

; STACK

STACK SEGMENT IDATA ; declare STACK segment
RSEG STACK
DS 80h ; reserve 128 bytes for stack

; MACRO DEFINITIONS

; RESET AND INTERRUPT VECTOR TABLE


CSEG AT 0
ljmp Main

org 2bh
ljmp TIMER2_ISR ; TIMER2 OVERFLOW INTERRUPT

; MAIN PROGRAM CODE

PM33 SEGMENT CODE ; declare CODE segment
RSEG PM33 ; select CODE segment
USING 0 ; using register bank 0

Main:
anl PCA0MD, #NOT(040h) ; clear Watchdog Enable bit

mov SP, #STACK-1 ; init stack pointer

clr A ; wait at least 1ms
djnz acc, $ ; wait 512us
djnz acc, $ ; wait 512u
acall Port_IO_Init
acall Timer2_Init ; initialize Timer2
setb EA ; enable global interrupts

sjmp $ ; spin forever

; MAIN SUBROUTINES
; INTERRUPT VECTORS

; SUBROUTINES

Port_IO_Init:

; P0.0 - Unassigned, Open-Drain, Digital
; P0.1 - Unassigned, Open-Drain, Digital
; P0.2 - Skipped, Open-Drain, Analog connected to
; P0.3 - Skipped, Open-Drain, Analog external crystal
; P0.4 - TX0 (UART0), Push-Pull, Digital
; P0.5 - RX0 (UART0), Open-Drain, Digital
; P0.6 - Unassigned, Push-Pull, Digital
; P0.7 - Unassigned, Push-Pull, Digital

; P1.0 - Unassigned, Open-Drain, Digital
; P1.1 - Unassigned, Open-Drain, Digital
; P1.2 - Unassigned, Open-Drain, Digital
; P1.3 - Unassigned, Push-Pull, Digital
; P1.4 - Skipped,Open-Drain,Analog ADC Input connected
; P1.5 - Unassigned, Open-Drain, Digital
; P1.6 - Unassigned, Push-Pull, Digital
; P1.7 - Unassigned, Push-Pull, Digital
; P2.0 - Unassigned, Push-Pull, Digital
; P2.1 - Unassigned, Push-Pull, Digital
; P2.2 - Unassigned, Push-Pull, Digital
; P2.3 - Unassigned, Open-Drain, Digital

mov P0MDIN, #0F3h
mov P1MDIN, #0EFh
mov P0MDOUT, #0D0h
mov P1MDOUT, #0C8h
mov P2MDOUT, #007h
mov P3MDOUT, #01Ch
mov P0SKIP, #00Ch
mov P1SKIP, #010h
mov XBR0, #001h
mov XBR1, #040h
ret
; Timer2_Init

; This routine initializes Timer3 in 16-bit auto-reload mode SYSCLK/12 as its time base. Exits with Timer2 started and Timer2 interrupts enabled.
;
Timer2_Init:SETB TR2
mov TMR2RLL, #020h ; auto-reload value
mov TMR2RLH, #0d1h
mov TMR2L, #020h ; initial value
mov TMR2H, #0d1h
SETB ET2 ; Timer2 Run control bit
SETB TR2 ; Timer2 interrupt enabled
ret


TIMER2_ISR:push PSW ; preserve registers
push acc
CLR LED
CLR TF2H ; CLEAR TIMER2 OVERFLOW FLAG
SETB AD0EN ; ENABLE ADC
ORL REF0CN,#0Ah; select voltage reference and enable
;bias generator

mov AMX0P, #004h
mov AMX0N, #01Fh
; ADC in single-ended mode P1.4 Analog I/P and GND negative I/P
mov ADC0CF,#70H
; Set SAR clock frequency ORL ADC0CF,#04h
; Data in ADC0H:ADC0L registers are left-justified.

CLR AD0INT ; CLEAR CONVERSION COMPLETE FLAG
SETB AD0BUSY ; Start of conversion
JNB AD0INT,$ ; Wait until conversion complete
CLR AD0EN ; Disable ADC
CLR AD0BUSY

anl REF0CN,#11111101b; Turn off Bias Generator
mov ADC_READING, ADC0H ; copy MSB of ADC0 result into
; ADC_READING
mov ADC_READING+1,ADC0L; copy LSB of ADC result into
; ADC_READING
SETB LED

TIMER2_ISR_END:
pop acc
pop PSW

reti


; End of file.

END