Dear All,
AOA

Using Fail safe Bias resistors,We can keep the Rs485 in known state...
SO
If Frame is more than 2 bytes long and after each Bytes Sender(driver)takes a software delay (with keep the DE pin high and RE pin Low), just to let receiver to consume the byte sent,
ON the other end if Receiver has consumed the byte and waiting for next Byte,In this situation, Receiver will be wait for next Start bit(0)Logic Low.

Question are:
1)Can Driver assert software delay between bytes of Frame to let the receiver to consume the byte?
2)When DE is High,But Driver is not actually sending bytes,What is state of Bus,it will be Logic High,SO Is is due to Driver last state after byte sent OR because of Fail-safe resistor?