I'm not sure what you mean, Richard.

A detailed look at the hardware guide, part of the "bible" by which 805x designers work out their hardware would probably be beneficial. That's available here, on this site. There are numerous schematics published on the www that will illustrate how this is done. All you have to do is search a little bit.

If you attach external memory to an 805x, using the "usual" signals, i.e. address lines to address lines, and data lines to data lines, the only issue is that you have to latch the low order addresses with, say, a 74HC573 or the like. That will snag the appropriate signals from P0 in order to become the low-order address buffer/latch. You then attach P0 to the data lines as well, and everything should function just as you'd like. High order addresses live on P2. ALE is used to operate the gate on the '573. the nRD signal is intended to enable the RAM output buffers and the nWR signal is intended to drive the nWE signal on the RAM. You will have no real opportunity to do anything wrong until you attempt to attach more than one external device.

How could you screw up the ALE? It's an output, and the one and only '573 will see it as an input.

RE