| ??? 06/13/01 13:53 Read: times |
#12443 - RE: connect 74HC374 to the bus of 51 series |
You must map the 374 into the memory of the UPC somehow. This could be done by ANDing it to some address together with the /WR signal from the 51. To be more specific: put A15 and A14 on the inputs of a 74HC00, the output of this gate goes to the two inputs of a second gate of the HC00. The /WR signal goes to the two inputs of the third gate. Now connect the output of the second gate and the third gate to the inputs of the fourth gate and out comes the LATCH ENABLE signal which must be negative to strobe.
Or make it more simple and take a PAL. Put as many addressinputs as you want (the more inputs the more specific the decoding will be). and make a statement like: /LE=A15*A14*A13*A12....A8*/WR |
| Topic | Author | Date |
| connect 74HC374 to the bus of 51 series | 01/01/70 00:00 | |
| RE: connect 74HC374 to the bus of 51 series | 01/01/70 00:00 | |
| RE: OR | 01/01/70 00:00 | |
| RE: connect 74HC374 to the bus of 51 series | 01/01/70 00:00 | |
| RE: connect 74HC374 to the bus of 51 ser | 01/01/70 00:00 | |
| RE: connect 74HC374 to the bus of 51 ser | 01/01/70 00:00 | |
| RE: connect 74HC374 to the bus of 51 ser | 01/01/70 00:00 | |
| Embedded market share of Intel 8052 | 01/01/70 00:00 | |
| RE: Embedded market share of Intel 8052 | 01/01/70 00:00 | |
RE: Embedded market share of Intel 8052 | 01/01/70 00:00 |



