The fifth ad is for ST (formerly Waferscale Intergration) PSD products, as a user of these I fail to see how this is a solution to expanding ram beyond 64Kb? . Other than using the inbuilt CPLD's to do paging with external ram chips.

To expand beyond 64Kb with a normal 8051 variant then you have to resort to paging, using one or more I/O lines as additional address lines to the ram address decoder, so that you can have n x 64k pages, you need to keep a track of which bank you are using with your software.

Some C compilers (IAR for example) support paging of memory.