Peter, Martin:

I have the solution for the next generation but for these thousands of boards already in the field and "working" by the definition of my predecessor (only fails once a month), the only socketed components are the controllers. In addition, this design from hell has 2 uCs with all port pins parralleled, so the delay to switch to and from ERAM is much less than the delay communicating between the uCs to switch bus access away from the other processor.

I am desperately trying to find a way to "declare EDATA" maybe by manhandling bankswitching or some such way. It may, after all come out that I have to do it without any automatic safeguards and if that has to be I will cry myself to sleep and get on with it in the morning.

Not having fun,

Erik