One suggestion based on using uCs with NO external memory: Make the bus P0 of all processors. Make each module request bus access on one of the wires going to P2 of your busmaster. Use some P1 pins as bus control signals.
Another: equip each board with a DPM. At powerup write zero to the first 2 bytes of the low half of the dpm. Do the same in the high half of the dpm. Put the chip selects of the other side of the DPM on the bus. When either module has data to send it will write to the low half: first the data starting in location 3, then the receivers address and data length at the start. The busmaster which has access to all DPMs will then transfer the data to the high half of the receivers DPM, again writing address and length last. When the transfer is complete, the busmaster will clear the first bytes of senders DPM. When receiver has taken the message, it will clear the first bytes of the high half.

dont be too BUSy, have fun

Erik