| ??? 03/07/07 12:36 Read: times |
#134455 - Somewhat? OK, then try again Responding to: ???'s previous message |
Ok with Mr Chinzei clarification matter is somewhat clear to me I see, I didn't answer to this question. (2) It is a minimu 8 clock cycle so more no of clock cycle can also be given? then how SC/MMC card will know that these clock cycle are not for clocking in next instrcuction ? It's just 8 clocks, no more, no less. 5.12 Clock Control (ProdManRS-MMCv1.3.pdf, p5-7)
After the last SPI bus transaction, the host is required to provide eight clock cycles for the card to complete the operation before shutting down the clock. The state of the CS signal is irrelevant throughout this eight-clock period. Tsuneo |
| Topic | Author | Date |
| Memory Cards - SD/MMC - Questions | 01/01/70 00:00 | |
| Which manual are you referring? | 01/01/70 00:00 | |
| Nice response - | 01/01/70 00:00 | |
| Same Sandisk Manual | 01/01/70 00:00 | |
| Somewhat? OK, then try again | 01/01/70 00:00 | |
| Please give link | 01/01/70 00:00 | |
Already shown in my previous post | 01/01/70 00:00 |