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08/16/01 08:47
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 		 #14138 - RE: interrupt response time differences
For now, I am primarily interested in TIMER OVERFLOW interrupts, which of course allways occur in the same phase.

Instruction RETI takes 2 cycles. Worst instruction MUL takes 4 cycles. There can be a MUL after a RETI, so the total time can be 6. On the other hand, it can be as low as 1, so the maximum responce time differce is 5.

Is this correct?

Best regards

Lennart


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TopicAuthorDate
interrupt response time differences            01/01/70 00:00      
RE: interrupt response time differences            01/01/70 00:00      
RE: interrupt response time differences            01/01/70 00:00      
RE: interrupt response time differences            01/01/70 00:00      
RE: interrupt response time differences            01/01/70 00:00      
RE: interrupt response time differences            01/01/70 00:00      

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