1. This has historical background.
The self-rewritable FLASH in '51 was introduced by Philips, in the P89C51Rx+. In this model, the timing of the FLASH write operations was accomplished simply by program loops, which of course depends on the oscillator frequency - that's why it was important to enter it for the programming algorithm (IAP API). This, as a relict remained even in the newer P89C51Rx2, although this already could time the write operation also from an internal (hidden for the user) timer.

The Temic/Atmel version of RD2 had always an internally-timed FLASH write algorithm, so it never needed to enter the frequency for the IAP API nor ISP.

2. During the FLASH programming, it is not possible to fetch instructions from the programmed FLASH (i.e. the lower part of memory, where the interrupt vectors reside). If an interrupt occurs in that moment, it fetches a nonsense instruction code and will run away.
This is why it is necessary to disable interrupts when FLASH write operations are going to be performed via IAP.

There is a similar problem with the watchdog. The default IAP code in AT89C51RD2 does not refresh the watchdog, so if you are using any form of watchdog, you better make sure you refresh it before the IAP API call and make sure that the watchdog timeout is longer than the longest time spend in the IAP code (this is AFAIK not easy to determine exactly, but at least an estimate can be derived from the programming times given in the datasheet).

In this respect, the P89V51Rx2's solution is superior to all other RD2s^* - as the boot FLASH is FLASH, a custom bootloader/IAP code can be written, which can handle both interrupts and watchdog. The only problem is, that Philips/NXP does not provide the documentation to do so, shame on them.

JW


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* I am not familiar enough with the Winbond and Macronix RD2s to claim the same for them - so this is valid for the more common Temic/Atmel and Philips/NXP only. The 'V' is, as I said already many times, SST... :-)