Does this topic continue from this one?

"SPI interrupts not firing"
http://www.8052.com/forum/read.phtml?id=146929

Then, is your 'F41x module a SPI slave as you said in this topic?
http://www.8052.com/forum/read.phtml?id=146932



On the master side, the SPI transfer starts immediately when the command is sent to the SPI register (SPI0DAT). On the slave side, however, the SPI interrupt fires when the transfer finishes. Also you have to count in the execution time for the command handling on the slave side.

It takes so long until the code execution reaches to "SPI0DAT = my_data;", after the SPI ISR is evoked. The next transfer has already started on the master side, when you set new data to SPI0DAT on the slave side. Then, the 'command' byte sent by the master loops back to the master as the 'answer'.

Master:       send command         send dummy byte
                V                   V
       MOSI:  ___X  command    X_____X   dummy     X____
       MISO:                      ___X  command    X__
       SCK :  ___|_|_|_|_|_|_|_|_____|_|_|_|_|_|_|_|_____
                                V         ^
Slave :                      interrupt    |send answer
                                |<------->|
                                  command handling

A simple solution is constant delay on the master side.
On the SPI master side ('F310?), insert enough delay before the master sends a dummy byte to retrieve the answer, so that the slave finishes the handling of the command.

Master:       send command    delay       send dummy byte
                V |<--------------------->| V
       MOSI:  ___X  command    X_____________X   dummy     X____
       MISO:                      ___________X   answer    X__
       SCK :  ___|_|_|_|_|_|_|_|_____________|_|_|_|_|_|_|_|_____
                                V         ^
Slave :                      interrupt    |send answer
                                |<------->|
                                  command handling

Or, implement a protocol on the slave side, as follows
Slave:
0) While no command is handled, the SPI ISR returns 'IDLE' byte
1) Receive a command byte in the SPI ISR
2) Handle the command in the main loop
3) While handling the command, the SPI ISR returns 'BUSY' byte
4) When the command handling finishes, the SPI ISR returns 'READY' and data

Master:       send command      send dummy byte
                V                 V                  V                 V
       MOSI:  ___X  command    X___X   dummy     X_...X   dummy     X___X   dummy     X__
       MISO:  ___X    IDLE     X___X    BUSY     X_...X   READY     X___X   answer    X__
       SCK :  ___|_|_|_|_|_|_|_|___|_|_|_|_|_|_|_|_...|_|_|_|_|_|_|_|___|_|_|_|_|_|_|_|__
                                V                    ^
Slave :                      interrupt               |send answer
                                |<------------------>|
                                  command handling on main loop

Tsuneo