Maxim <www.maxim-ic.com> doesn't list the part number you cite on their web site.

Here's a quote from the DS89C450-K00 (The only DS89C450 EVB they admit to producing) datasheet, describing the function of the CPLD:



This information is provided in addition to an RTL listing of the CPLD. If you do have a different board than that, I suspect the corresponding information is given.

Latching the low-order addresses on P0 is only of benefit if you are using an external address bus. Mapping both code and xdata into the same space is only of use if you use external program and data memory. If you can "get by" with only the 1kB of on-board XRAM, you won't, AFAIK, need the CPLD.

I've not purchased this particular board because it lacks certain features I want to have available. I've built my own "eval kit" using a "standard" external address/data bus using discrete "family" logic, in which I have co-mapped code and data space. The components that will do the job are 74HCT373/573, HCT00, and an external crystal oscillator.

Some people will tell you you must use an external reset supervisor. I recommend caution, as the MCU also wants to drive RESET on occasion. It's easy to force a latchup in RESET if you're not careful. You must be certain that both the MCU and your external circuitry don't attempt to drive RESET at the same time, as most supervisors aren't compatible with actively driven RESET aside from their own.

From where I sit, the jury is still out on that one, as the MCU has the watchdog and brownout detection cicuitry built in.

I'd recommend you use a power supply sufficient to ensure you have a rise time on Vcc that's significantly shorter than 10 ms. I'd also recommend you ensure that your Vcc fall time, when the power is shut off, is less than 1 ms. That means you need a pretty hefty supply, and a switch that kills Vcc, and not just shuts its off, along with relatively low capacitance on Vcc. I used an SPDT switch with the pole opposite Vcc tied to GND. An SCR might be better. In either case, a low-impedance discharge path for the Vcc capacitance must be provided.

Be sure that, if you provide any external memory bus at all, you support all available modes of operation. Maxim failed to do that on their board. The fastest operating mode for an external memory bus on the DS89C4x0 is Page Mode 1, which multiplexes both high and low address bytes from P2 while leaving data stabile on P0. With fast external RAM, such as the 15 ns 64k x 8 SRAM I've used, an ERPROM or FLASH can be transferred into the SRAM, whereupon the EPROM is disabled, and control transferred to the external SRAM. That, alone, is sufficient justification for the CPLD, as CPLD's are typically quite a lot faster than 'HCT logic.

RE