Hi,

We are trying to develop some TUSB3410 related code on IAR 7.20.
We are having issues with xcl file when we use the data model as large.We are getting the error as
Fatal Error[e72]: Segment CODE must be defined in a segment definition option (-Z, -b or -P)
Can someone help us understand what is the problem?
And the TUSB3410 specification is in the below link
http://rapidshare.com/files/898...0.pdf.html

...////////////////////////////////////////////////////////////////////////////////
//
//   lnk51ew_TUSB3410.xcl:
//   ==========
//         Linker command file used in the IAR Embedded Workbench IDE for
//         Silicon Laboratories C8051F35x device
//
//   Revision control system
//       $Id: lnk51ew_C8051F35x.xcl 1.2 2005/10/13 14:16:07Z matsp Exp matsp $
//
//  Important:
//    Data cannot be located at address zero, this address is reserved for
//    the null pointer.
//
////////////////////////////////////////////////////////////////////////////////

// Revision History:
//
//       $Id: 1.3 2008/02/06 17:27: Mukund Jampala: ESN Technologies
//

////////////////////////////////////////////////////////////////////////////////
//
// Variables (used by lnk_base.xcl)
// ================================
//
// Segment limits
// --------------
//
//
//    IDATA
//
-D_IDATA_END=0xFF              // Last address of Idata memory (0xFF for 8052 and 0x7F for 8051)
//
//
//    PDATA
//
/// Mukund Done
-D_PDATA_START=0xF801          // First address for PDATA memory.
-D_PDATA_END=0xF8FF            // Last address for PDATA memory.
///-D_PDATA_START=0xFC00          // First address for PDATA memory.		// FREE memory region in XDATA Space i.e. on 2K RAM
///-D_PDATA_END=0xFCFF            // Last address for PDATA memory.
//
//
//    IXDATA
//                              * TUSB3410 Xdata:
//                              * XData on the chip is defined form 0xF800 - 0xFFFF
//                              * The range from 0xF800 - 0xFF7F is occupied by SRAM (2K - 128) bytes
//                              * The range from 0xFF80 - 0xFFFF is occupied by MMR Registers (Memory mapped Registers) (128 Bytes)
//
/// Mukund Done
-D_IXDATA_START=0xF801        // First address of on chip XDATA memory.
-D_IXDATA_END=0xFF80          // Last address of on chip XDATA memory. (TILL SRAM End)
//-D_IXDATA_END=0xFFFF          // Last address of on chip XDATA memory. (Till MMR End - Complete 2K)
//
//
//    XDATA
//
/// Mukund Done
-D_XDATA_START=_IXDATA_START       // First address of XDATA memory.
-D_XDATA_END=_IXDATA_END           // Last address of XDATA memory.
//
//
//    CODE
//
//                                * TUSB3410 Code:
//                                * TUSB3410 chip has 16kb RAM memory used for CODE AREA
//                                - CODE:0x0000-0x4000//
/// Mukund Done
-D_CODE_START=0x0000           // First address for CODE.
-D_CODE_END=0x3FFF             // Last address for CODE.
//
//
//    TINY CODE
//
/// ORG -D_TINY_CODE_END=0x0FF         // Last address for tiny code.
-D_TINY_CODE_END=0x7FF         // Last address for tiny code.
//
//
//    NEAR CODE
//
-D_NEAR_CODE_END=_CODE_END        // Last address for near code.
//
//
//    FAR DATA
//
-D_FAR_DATA_NR_OF_BANKS=0   // Number of banks in far data memory.
-D_FAR_DATA_START=0         // First address of far memory.
-D_FAR_DATA_END=_XDATA_END  // Last address of far memory.
//
//
//    FAR CODE
//
-D_FAR_CODE_START=_CODE_START  // First address for far code.
-D_FAR_CODE_END=_CODE_END      // Last address for far code.
//
//
//
// Special SFRs
// ------------
//
//
//    CODE bank setup
//
-D_FIRST_BANK_ADDR=0x10000
-D_NR_OF_BANKS=0x10
//
//
//    Register bank setup
//
-D?REGISTER_BANK=0             // Default register bank (0,1,2,3).
-D_REGISTER_BANK_START=0       // Start address for default register bank (00,08,10,18).
//
//
//    PDATA page setup
//
-D?PBANK_NUMBER=0F	           // high byte of 16-bit address to the PDATA area
-D?PBANK=A0                    // Most significant byte in MOVX A,@R0. (0xA0 is sfr P2)
-D?PBANK_EXT=0xEA              // Most significant byte in MOVX A,@R0. (0xEA is for Dallas DS80C390)
//
//
//    Virtuel register setup
//
///-D_NR_OF_VIRTUAL_REGISTERS=0x20

-D?VB=20                       // Used to refer to BREG as byte.
//
//
////////////////////////////////////////////////////////////////////////////////


//*--------------------------------------------------------------------
//* TUSB XDATA Definition
//* This defn applies to both the 3410 and 5x52
//*--------------------------------------------------------------------

-Z(XDATA)TUSB_NO_EXTERNAL_RAM_SEG=0000-F7FF // NO MEMORY IN THIS RANGE

//*--------------------------------------------------------------------
//* Define BOOTCODE segments
//*--------------------------------------------------------------------
//-Z(XDATA)TUSB_BC_OEP1_BUFFER_SEG=F800-F83F   // OEP1 data buffer   ( 64 bytes)
-Z(XDATA)TUSB_BC_DEVCFG_DESC_SEG=F840-F8FF   // device/config info (192 bytes)
//-Z(XDATA)TUSB_DEFVARS_SPC1_SEG=F900-FAFF   // program VAR space  (512 bytes)
-Z(XDATA)TUSB_BC_STRING_DESC_SEG=FB00-FB7F   // string descriptor  (128 bytes)
//-Z(XDATA)TUSB_DEFVARS_SPC2_SEG=FB80-FDE7   // program VAR space  (616 bytes)

-Z(XDATA)TUSB_OEP0BUFFER_SEG=FEF0-FEF7      // 8-byte data output endpoint 0
-Z(XDATA)TUSB_IEP0BUFFER_SEG=FEF8-FEFF      // 8-byte data input endpoint 0
-Z(XDATA)TUSB_SETUPPACKT_SEG=FF00-FF07      // 8-byte setup packet
-Z(XDATA)TUSB_OEP_EDB_SEG=FF08-FF1F         // 3 output endpoint configuration
-Z(XDATA)TUSB_IEP_EDB_SEG=FF48-FF5F         // 3 input endpoint configuration
-Z(XDATA)TUSB_EP0_EDB_SEG=FF80-FF83         // EP 0 descriptor block

//*--------------------------------------------------------------------
//* Define LOADCODE segments  (downloaded code)
//*--------------------------------------------------------------------
-Z(XDATA)DEV_EPX_BUFFS_SEG=FDE8-FEEF        // I/O EP buffs (2*(2x64) + 8)
-Z(XDATA)DEV_EP0_BUFFS_SEG=FEF0-FEFF        // I/O EP 0 buffs (16 bytes)
//-Z(XDATA)DEV_EP0_OBUFF_SEG=FEF0-FEF7        // Out EP 0 buffer (8 bytes)
//-Z(XDATA)DEV_EP0_IBUFF_SEG=FEF8-FEFF        // Inp EP 0 buffer (8 bytes)

-Z(XDATA)DEV_EP0_SETUP_SEG=FF00-FF07        // 8-byte setup packet
-Z(XDATA)DEV_OEP_DESCS_SEG=FF08-FF47        // Output EP configs 1-7
-Z(XDATA)DEV_IEP_DESCS_SEG=FF48-FF7F        // Input  EP configs 1-7
-Z(XDATA)DEV_EP0_DESCS_SEG=FF80-FF8F        // I/O    EP configs 0


////////////////////////////////////////////////////////////////////////////////
//
// Include the lnk_base command file
// =================================
//
//
-f lnk_base.xcl
//
////////////////////////////////////////////////////////////////////////////////
...

Regards,
Mahesh