Few 805x's are too fast for the old, and, BTW, obsolete, DRAMs. However, with a bit of external logic to latch the low addresses at the falling edge of ALE and upper address using nRD ANDed with nWR as nCAS, you might "get away with" such a trick. It might be necessary to delay the nCAS strobe so that nWR will arrive before nCAS at the DRAM. With several clock ticks per cycle, this shouldn't be difficult. I fail to see the point, however, when, as Michael Karas has pointed out, many modern 805x's have a full complement of FLASH as code space and when there are CMOS 64Kx8, and larger, SRAMs available for use as data memory. The power consumption alone warrants the use of a latch, such as a 74??573, which is easier to route than a '373.

RE