??? 01/17/09 05:38 Read: times |
#161575 - It's a core, intended for FPGA, not a chip. Responding to: ???'s previous message |
Andy Neil said:
At least with SFR space, you don't have the overhead of loading the DPTR...
Richard Erlacher said:
Further, some instructions can be executed concurrently or even out of order, if you're inclined to fiddle with the logic. Sounds a bit advanced given the reason for the original post: Christian Meier said:
we don´t know how to push the signal "ext_ram_en" to "1". (Signal in 8052.vhd) It would take just about as much fiddling to put the CAN controller in external memory space, given that it's going to be in FPGA either way, as it would to put it in SFR space. How much fiddling they do depends on their level of industry. If they just want to "get by" they'll modify the core as little as possible. If they want a really good grade, well, they'll do more. I simply pointed out that they don't have to figure out how to make external memory space work, and, since the SFR space is already enabled ... well ... you get the idea. RE |