Hello Alex,

Mayer's code is a VHDL source of a behavioural 8051 core, found in
Hamburg University VHDL repository.
This is basicaly a simulation model. You need to modify all time
references and initialisations for logic synthesis.
Peripherics are not complete. Only one mode for UART and timer.
But timings are correctly performed with 12 microcycles by cycle.

I have read informations on the number of FPGA cells needed for 8051
implementation. You need between 2000 and 3000 cells.
Have your Altera chip these cells ? I have planed a Virtex chip for
this purpose and 8051's internal RAM-ROM outside XCV component.

It is difficult to send you directly a message. I have tried today to send
you an e-mail, it has returned unsend. If you want a copy of files
please give me a permanent e-mail adress, for posting attached files.

Best regards,