Modified new code according to Jan Waclawec's suggestion as follows

      cseg  AT  0000H
      jmp   codstr
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      cseg  AT  0050H
codstr:                 ;(program code starts here)
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      setb  QH          ;(set Port as input)
      setb  CLKINH      ;(prevent clock signal's rising edges accidently)
      clr   CLKP        ;NEWLY ADDED!!! (clear clock signal initially)
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      mov   WAITFW,#32  ;(enough to meet all propagation time)
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prgstr:                 ;(main program loop starts here)
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      clr   SHLD        ;(reset SH/LD input of 74HC165 to get parallel inputs to register)
      call  WFW         ;(wait for a while for progopation time)
      setb  SHLD        ;(set SH/LD input of 74HC165 to read parallel inputs. this freezes the register)
      call  WFW         ;
      clr   CLKINH      ;(reset Clock Inhibit input of 74HC165 to enable clock input of 74HC165)
      call  WFW         ;

      mov   PLSCNT,#8   ;(rise clock for 8 times)

pr1:  mov   C,QH        ;(3)ROW CHANGED!!!(..then read the serial output)
      rlc   A           ;(4)ROW CHANGED!!!
      setb  CLK         ;(1)(set Clock input of 74HC165, rising edge of clock..)
      call  WFW         ;(2)
      clr   CLK         ;(5)
      call  WFW         ;(6)
      djnz  PLSCNT,pr1  ;(7)(8-bit completed?)
      mov   FRST8,A     ;(8)(get first 8-bit)

      mov   PLSCNT,#8   ;(same as the first part)

pr2:  mov   C,QH        ;(3)ROW CHANGED!!!
      rlc   A           ;(4)ROW CHANGED!!!
      setb  CLK         ;(1)
      call  WFW         ;(2)
      clr   CLK         ;(5)
      call  WFW         ;(6)
      djnz  PLSCNT,pr2  ;(7)
      mov   SCND8,A     ;(8)(get second 8-bit)

      setb  CLKINH      ;(disable clock input of 74HC165)
      call  WFW         ;
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      jmp   prgstr      ;(end of main loop)
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WFW:  djnz WAITFW,$     ;(simple code to wait for a while)
      mov  WAITFW,#32
      ret
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        DSEG    AT  30H
FRST8:  DS      1
SCND8:  DS      1
WAITFW: DS      1
PLSCNT: DS      1
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QH	EQU	P3.5
SHLD	EQU	P3.4
CLK	EQU	P3.3
CLKINH	EQU	P1.2
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        end