void ext_int_0(void) interrupt 0 	;external interrupt 0
{			
#pragma asm		;SRC directive	must be active to use this.
    clr EA		;disable interrupts
	
    jb	PS2_DATA, the_end	;start bit must be 0
	
    mov R0, #08		;bits in a byte counter
    clr A
getbyte:
; look for +ve edge
    wait_till_clk_high:	jnb PS2_CLK, wait_till_clk_high	;==> while(clock == low);
; look for -ve edge		
    wait_till_clk_low:	jb PS2_CLK, wait_till_clk_low	;==> while(clock == high);
; little delay
    mov R1, #8
    djnz r1, $	;reading LSB 20us after -ve edge
; okay go on...
    mov c, PS2_DATA
    rrc	a				;LSB is clokced in first
    djnz  R0,getbyte	;repeat for whole byte	
/*----now byte is in ACC----*/	;we have only 900 us to waste
finally:
    mov R0, write_counter	;i.e. #0x00
    movx @R0, A		;save ACC to external RAM (8-bit addr)
    inc write_counter

    mov	A, write_counter	
    xrl	A, #200		;write_counter: 0-199 are valid 
    jz	pwned		;clear write_counter if = 200
    ajmp wait		;else exit ISR 
    pwned:	mov	write_counter,#0		;clear write_counter

wait:	mov R1, #200	 ;waste ~400us to allow the parity & stop bits to pass...
    djnz R1, $		 ;MUST WASTE MIN 224us
    mov R1, #200	 
    djnz R1, $		

the_end:  setb EA
#pragma	endasm
/*===========================================================*/	;end of inline ASM
};ISR ends

 

some registers do need to be pushed: ACC, R0, R1, PSW, DPTR etc but almost half are redundant.
Optimization level: 8:reuse common entry code

does memory model & assigning a particular register bank to ISR have an effect on this?