This routine comes from Rigel corporation :


; Pwm runs on Rigel's R31JP board (using the 80C51/80C52
; microcontrollers. It uses Timer 0 interrupts to generate
; PWM signals on P1.0.
; -----------------------------------------------------------------------------
crlf equ 115h ; a
getbyt equ 011eh ; a, b
getchr equ 0121h ; a
prthex equ 013fh ; a, r2
sndchr equ 0148h ; a

; -----------------------------------------------------------------------------
; --- constants ---
MAXTICKS equ 10
; --- register use ---
; r4 : OUTPUT Boolean value of output bit
; r5 : DUTYCYCLE holds 0..255 (0% to 100%)
; r6 : TIME_OUT current time in duty cycle
; r7 : TICKS software timer ticks

org 8000h

; --- initialize Timer 0 ---
anl TMOD, #0F2h
orl TMOD, #002 ; TMOD low nibble is 2 (Mode=2, reload timer)
mov TH0, #20h ; change for a different period
setb ET0 ; enable Timer 0 interrupt (IE bit)
setb TCON.4 ; TR0 ; start Timer 0 (TCON bit)
clr TCON.5 ; TF0 ; Timer 0 overflow flag (TCON bit)
setb EA ; finally... master interrupt enable (IE bit)


; --- main loop ---
lcall T0Isr
start:
lcall getbyt ; wait for keyboard
mov r5, a ; r5 is DUTYCYCLE
lcall prthex
lcall crlf
sjmp start

clr EA ; disable all interrupts
clr TR0 ; Timer 0 off
ljmp 0 ; return to monitor

; --- T0 interrupt service routine ---
T0Isr:
push acc
inc r7 ; r7 is the TICKS
cjne r7, #MAXTICKS, T0IsrDone
mov r7, #0
lcall Pwm
T0IsrDone:
pop acc
reti

; --- PWM routine ---
Pwm:
dec r6 ; r6 is TIME_OUT
cjne r6, #0, PwmDone ; done if no time out

cjne r5, #0, Pwm01 ; handle DutyCycle=0 separately
clr P1.0
ret
Pwm01:
cjne r5, #0FFh, Pwm02 ; handle DutyCycle=255 separately
setb P1.0
ret
; 0 < DutyCycle < 255
Pwm02:
cjne r4, #0, SetOutput ; r4 is the Boolean output state

mov a, #'0'
lcall sndchr ; debug

mov r4, #0FFh
mov a, r5 ; TIME_OUT = 100h-DUTYCYCLE
cpl a
mov r6, a
clr P1.0 ; output bit is P1.0
ret

SetOutput:
mov a, #'1'
lcall sndchr ; debug

mov r4, #0
mov a, r5 ; TIME_OUT = DUTYCYCLE
mov r6, a
setb P1.0 ; output bit is P1.0
PwmDone:
ret

; --- redirected interrupt vector ---
org 0FF04h
ljmp T0Isr