| ??? 04/18/10 12:29 Read: times |
#175105 - Benefit of a higher SYSCLK ? |
Refer the code from Silabs examples : F12x_ADC0_ExternalInput_Mux.c
The ADC0 conversions are designed to be started once every 20uS by the use of Timer 2 overflow. And the acquired mV data sent to Serial port at 115200 baud rate. I was reading the code and found that they had used the PLL to multiply the base frequency of 24.5 MHz ( internal clock )by a factor of 2 to get a SYSCLK of 49 MHz. I noticed that the 20us conversions as well as 115200 baud could be achieved without jacking up the base clock to 49MHz. So why was it done ? Do we stand to gain any advantage of running at 49 MHz compared to 24.5MHz ? Or am I missing out something in this process ?? Raghu |
| Topic | Author | Date |
| Benefit of a higher SYSCLK ? | 01/01/70 00:00 | |
| Depends | 01/01/70 00:00 | |
| Use what you pay for... | 01/01/70 00:00 | |
| Quite common to halt/sleep core during ADC capture | 01/01/70 00:00 | |
| Seems to be a demo of various items... | 01/01/70 00:00 | |
Another Strong Reason... | 01/01/70 00:00 | |
| if you set it high enough ... | 01/01/70 00:00 |