| ??? 08/09/10 17:50 Read: times |
#177911 - maybe not totally related Responding to: ???'s previous message |
Be aware that the single-clock SILabd chips, when configured as quasi, do not have the "brief heavy pullup" multi-clock chips have.
Erik |
| Topic | Author | Date |
| Pulse degradation | 01/01/70 00:00 | |
| For many purposes, slow flanks are not a problem | 01/01/70 00:00 | |
| Slew-rate limiting | 01/01/70 00:00 | |
| Extending SiLabs TestBoard I/O | 01/01/70 00:00 | |
| Solved.. | 01/01/70 00:00 | |
| piggy back PCB? | 01/01/70 00:00 | |
| maybe not totally related | 01/01/70 00:00 | |
| Quite related and valuble | 01/01/70 00:00 | |
| Brief Heavy or Not | 01/01/70 00:00 | |
| Series resistors will do the trick! | 01/01/70 00:00 | |
| Pro vs Amatuers | 01/01/70 00:00 | |
| I'd like to rephrase | 01/01/70 00:00 | |
| Theory first, then lots of testing | 01/01/70 00:00 | |
| Environment... | 01/01/70 00:00 | |
! Amused | 01/01/70 00:00 |