I would like to suggest that the "Skip Registers" were designed into the later SiLabs chips as a bandaid on top of the already injured and handicapped priority crossbar. Just adding these skip registers by the designers and architects is almost as good as an admission that the crossbar was a crippled concept. But I suppose they had to keep the thing because of feature differentiation and compatibility to earlier part families.

In terms of usage model I actually prefer that used by the C8051F226 part where each peripheral I/O signal is tied specifically to a particular port pin. (That's the way the original Intel part was done and it's really easy to understand).

I would only support the two to four MUXed I/Os at each port pin, such as has been suggested elsewhere in this thread, if there were more on-board I/O signals than port pins to allocate them all. Then the 2-1, 2-2 or 2-3 mux at each pin get designed to permit the user to select a reasonable selection of peripherals for their application.

Michael Karas