The purpose of Watchdog reset hardware is to bring sanity back into the system by resetting it , when the software looses control either due to a bug or due to some hardware interference. So it is imperative that the watchdog hardware should be external to the CPU ( or atleast an independent logic unit inside the microprocessor).

The software is expected to periodically reset the Watchdog timer so that watch dog hardware does not generate reset signal for the CPU. So, a good place to keep the code for taking care of watchdog is in the Mainloop of any program where control comes periodically.

SOme microcontrollers do provide WDOG hardware on the processor(for ex. PIC - I am not aware of any 8051 variant which provides on chip WDOG hardware.) But all these provide a bit , by setting which the Watchdog hardware can be disabled. Is This right? If software looses control in such way ( say an extra POP instruction executed somewhere), the watchdog may get disabled. Why are these processors providing this 'STOP WATCHDOG' Facility? Does anybody have any explanation?

Thanx
k.Ganeshan