Hi Bert,

When you say "it seems to cause a reset", where exactly in the code is this reset generated and what kind of reset is it? (I *do* assume you have stepped through your code with the debugger)

Some comments:

WriteFlashByte:				;Write the byte in accumulator to flash address in dptr
		push	acc
-->		mov	RSTSRC,#00h	;Disable VDD monitor as a reset source      <-- Why, if you are going to enable it again in the very next line?
		mov	RSTSRC,#02h     ;Enable VDD Monitor as a reset source
		mov	VDM0CN,#0A0h	;Enable VDD monitor and high threshold

WFBc:		mov	r7,#0		;Wait for VDD monitor to stabilize
		djnz	r7,$
   		mov	a,VDM0CN
   		jnb	acc.6,WFBc	;Wait for the VDD voltage to be high enough
-->		mov	RSTSRC,#02h	;Enable VDD Monitor as a reset source       <-- Superfluous, this has been done already
		mov	FLKEY,#0A5h	;Key sequence 1                             
		mov	FLKEY,#0F1h	;Key sequence 2                              > This is in the wrong order as compared to the datasheet procedure
      		mov	PSCTL,#1                                                    /
-->		mov	VDM0CN,#0A0h	;Enable VDD monitor and high threshold      <-- Superfluous, this has been done already
-->		mov	RSTSRC,#02h     ;Enable VDD Monitor as a reset source       <-- That's the third time!
      		pop	acc
		movx	@dptr,a
		mov	PSCTL,#0
		inc	dptr
		ret
 

Personally, I would do it something like this:

WriteFlashByte:				;Write the byte in accumulator to flash address in dptr
		push	acc
		mov	RSTSRC,#02h     ;Enable VDD Monitor as a reset source
		mov	VDM0CN,#0A0h	;Enable VDD monitor and high threshold

WFBc:		mov	r7,#0		;Wait for VDD monitor to stabilize
		djnz	r7,$
   		mov	a,VDM0CN
   		jnb	acc.6,WFBc	;Wait for the VDD voltage to be high enough
      		pop	acc
      		mov	PSCTL,#1
		mov	FLKEY,#0A5h	;Key sequence 1
		mov	FLKEY,#0F1h	;Key sequence 2
		movx	@dptr,a
		mov	PSCTL,#0
		inc	dptr
		ret


 

Kind regards,
Rob.