Hi,

Well there's a lot more to the circuit as it is now (I'm not a HW designer so I don't pretend to understand it all)

We have an 80C52 Micro and we need RW access to 64KEXTFLASH and 8KEXTRAM, and W access to a DAC and a DATALATCH as well as using every port pin there is.

We have A0-A13 connected to EXTFLASH address lines A0-A13 - 16K
We have A0-A12 connected to EXTRAM address lines A0-A12 - 8K

We have A14+A15 as input to a Decoder - such that:

a15 a14
0 0 - Y0 - enables RAM (READWRITE Address range 0000H-1FFFH)
0 1 - Y1 - enables DAC
1 0 - Y2 - connects to /CE of FLASH (WRITEONLY Address Range 8000H-9FFFH)
1 1 - Y3 - enables DATALATCH.

We have the 8051's /PSEN ANDed with /RD connected to /OE of FLASH - this allows both instruction fetch and read access to FLASH/'const code' data(?).
We use the decode of Y2 and /WR to allow programming of FLASH.

So I think this setup gives me:

0000-1FFF RW to EXTRAM
2000-3FFF PSEN to EXTFLASH (second 8K block)
4000-7FFF W to DAC
8000-9FFF W to EXTFLASH (first 8K block)
C000-FFFF W to DATALATCH

I think this might(?) work although I find this shared data/address space completely alien to me!
I may have missed some bits but that is essentially how I see it.

Kev