Allen makes an excellent point and there is a lesson to be learned.

That is that even after listening to someone's expert opinions on how to *approach* a project, *you* must go read the fine print of the microprocessor and chips manuals involved to confirm that the idea will work.

BACK TO YOUR CIRCUIT:
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Since the T0/T1 counter can only recongnize 1:0 transitions at 1/24th the clock rate, you might be led to think that a 24Mhz clock is the answer - with some adjustments to the timer.

Not necessarily. What I failed to mention was a digital trick used in the analog to digital conversion circuit.
Since your signal may not be running at a 50% duty cycle, your microprocessor may not see the transition at any crystal speed. The "trick* is to put a flip/flop to create a 50% duty cycle digital signal into the microprocessor. This flip/flop outputs a transition at every clocking edge of the signal resulting in a perfect 50% duty cycle output and a divide by two count rate.

And to stay away from the borders of Shannon's law, it would be better to have the microprocessor running a little faster than 12Mhz. While by the book, it could catch the 500Khz maximun signal coming into the microprocessor, the signal and crystal may be out of phase enough due to temperature etc. that you start to missing transitions. This phasing could result in Moirre type patterns and falsely signal much much lower frequencies. 18Mhz with the 50% duty cycle flip-flop circuit should make an improved solution.

Of course that's just how I'd approach it. You still have to prove it works.

Remember that the timer and counter values would have to be recomputed for both the new crystal rate and the lower input frequency on the counter input signal.

-Jay C. Box



-Jay C. Box