" P3.0 (RxD) as RS 
  P3.1 (TxD) as RW 
  P3.2 (_INT0) as EN 

  DATA EQU 090H"


1. You would minimize time for RW=0.
   Hold RW line high as long as possible.
   Pull it off only if you write to LCD -
   - see for start bit detection of ACE.
   (I assume P3.1 pin (TxD) is connected to
   Rx of PC too.)
2. I must repeat my question. What is the 
   reason of such design.
3. Gurus advice to you to use 4-bit interface.
4. Why you don't simulate HD44780U timing
   diagram such way ->

TETST_BF:
         CLR RS 
         SETB RW 
         MOV DATA,#0FFH 
LCDPOLL: 
         SETB EN 
         MOV A,DATA
         CLR  EN
         JB ACC.7,LCDPOLL 
;  CLR EN - commented out
;  CLR RW - commented out
         RET 
Think about your XTAL frequency and use NOPs
if it is necessary.
5. Test busy flag before another LCD addressing.

Vaclav