I'm looking all over for how to set-up an 8051(cygnal c8051f02x) parallel port to give information to a xilinx fpga(spartan).

I checked here, cygnal.com, google and a little on xilinx.

I'm pretty sure that I can use the AD0-7 and A0-7 pins for the addressing and data(add a chip in there for taking the first portion of the address from the ADs), but I'm not sure where to/how to control the flow. Would it be the WR/RD/ALE pins?

Thanks, sorry about the newb q.