Thanks to rob,werner,erik for there help

I am planing to design CPLD which will be interface to 89c52 through port
CPLD XILIX 9572 will be design in the follows :

Digital filter + two state machine for decoding logic. + 16 bit counter

State machine
1) A & B will be 2 inputs and up/down as a one output

2)A & B will be inputs and CLK as a one output

where A will be count and B will be direction.

THIS UP/DOWN AND CLK outputs will go to 16 bit counter.

The changes in input A & B will be
00->01->11->10->00 in one direction
00->10->11->01->00 in other direction


HOW DO YOU FIND IT I AM USING CPLD FIRST TIME ?