Guy:
Please note that the ISA bus to the CGA card is specifically NOT a multiplexed bus. The ISA bus has separated address and data lines. The CGA board being an 8 bit card has address lines A19->A0 for memory address and A9->A0 for I/O cycle.

You can save yourself some I/O pins by hard wiring the upper address bus for memory cycles. I believe that you would tie as follows:

   A19 -> H
   A19 -> L
   A17 -> H
   A16 -> H
   A15 -> H

I/O cycles can also have some address lines fixed during I/O cycle as listed below, but you would still need to drive these during memory cycle.

   AEN->L
   A9->H
   A8->H
   A7->H
   A6->H
   A5->L
   A4->H
   A3->H

Two additional things to note is that the CGA board will require the not oft used IOCLOCK signal on pin B20 and the OSC signal (14.318 MHz oscillator) on pin B30 of the ISA connector in orrder for an unmodified board to function correctly.
Good Luck !!!
Mike Karas