Ando now the listing with the generated code:

<pre>
A51 MACRO ASSEMBLER DIVIS DATE 24/10/02 PAGE 1


MS-DOS MACRO ASSEMBLER A51 V4.6
OBJECT MODULE PLACED IN C:TMPDIVIS.OBJ
ASSEMBLER INVOKED BY: A51 DIVIS.A51 OJ(C:TMPDIVIS.OBJ) PL(65535)

LOC OBJ LINE SOURCE

1 ;************************************************************************/
2 ;* */
3 ;* Scalable Mathematics: Division */
4 ;* */
5 ;* Author: Peter Dannegger */
6 ;* danni@specs.de */
7 ;* */
8 ;************************************************************************/
9 $nosb
10
0005 11 a_size equ 5 ;divident: 5 bytes
0002 12 b_size equ 2 ;divisor: 2 bytes
13
0000 14 ra0 equ r0 ;divident
0001 15 ra1 equ r1
0002 16 ra2 equ r2
0003 17 ra3 equ r3
0004 18 ra4 equ r4
19
0030 20 rb0 equ 30h ;divisor
0031 21 rb1 equ 31h
22
0005 23 rr0 equ r5 ;remainder
0006 24 rr1 equ r6
25
0007 26 ri0 equ r7 ;loop counter
27
32 +1 $rs
33 ;-------------------------------------------------------------------------
0000 34 scaldiv:
0000 E4 35 clr a
48+1+1 $rs
0001 FD 49+1 mov _regr, a ;clear remainder
54+1+1 $rs
0002 FE 55+1 mov _regr, a ;clear remainder
57 +1 $rs
0003 7F28 58 mov ri0, #a_size * 8
0005 C3 59 _scd1: clr c
74+1+1 $rs
0006 E8 75+1 mov a, _rega
0007 33 76+1 rlc a ;shift divident
0008 F8 77+1 mov _rega, a
82+1+1 $rs
0009 E9 83+1 mov a, _rega
000A 33 84+1 rlc a ;shift divident
000B F9 85+1 mov _rega, a
90+1+1 $rs
000C EA 91+1 mov a, _rega
000D 33 92+1 rlc a ;shift divident
000E FA 93+1 mov _rega, a
98+1+1 $rs
000F EB 99+1 mov a, _rega
0010 33 100+1 rlc a ;shift divident
0011 FB 101+1 mov _rega, a
106+1+1 $rs
0012 EC 107+1 mov a, _rega
0013 33 108+1 rlc a ;shift divident
0014 FC 109+1 mov _rega, a
124+1+1 $rs
0015 ED 125+1 mov a, _regr
0016 33 126+1 rlc a ;shift remainder
0017 FD 127+1 mov _regr, a
132+1+1 $rs
0018 EE 133+1 mov a, _regr
0019 33 134+1 rlc a ;shift remainder
001A FE 135+1 mov _regr, a
138 +1 $rs
001B 10D708 139 jbc cy, _scd2
157+1+1 $rs
001E ED 158+1 mov a, _regr
001F 9530 159+1 subb a, _regb ;test subtraction
166+1+1 $rs
0021 EE 167+1 mov a, _regr
0022 9531 168+1 subb a, _regb ;test subtraction
170 +1 $rs
0024 4009 171 jc _scd3
0026 172 _scd2:
190+1+1 $rs
0026 ED 191+1 mov a, _regr
0027 9530 192+1 subb a, _regb ;subtract
0029 FD 193+1 mov _regr, a
200+1+1 $rs
002A EE 201+1 mov a, _regr
002B 9531 202+1 subb a, _regb ;subtract
002D FE 203+1 mov _regr, a
205 +1 $rs
002E 08 206 inc ra0 ;set result bit
002F 207 _scd3:
002F DFD4 208 djnz ri0, _scd1
0031 22 209 ret
210 ;-------------------------------------------------------------------------
211 end



REGISTER BANK(S) USED: 0

ASSEMBLY COMPLETE, NO ERRORS FOUND