jay jay:
At the input side of the PLD in the simplest case you can use a D-type flip flop to buffer the async signal into the logic of the gate array. Clock this flip flop from the 40 MHz clock. Then run all of the internal logic in a sync type design off 40 MHz. Not that this is not a 100% safe design technigue. There is still always the small chance that the input D flip flop will go meta-stable when the async input signal changes state very close to the same time the clock active edge occurs.

There are two ways to further reduce the chance of the meta-stable condition causing the problems of async signals. One way it is to use two D-type flip flops in series to register the signal through two stages. The second way is to further qualify the input signal with the circuit called a 'digital one shot" that detects the two edges of the async input signal and gives a one clock wide pulse after the edge of the input signal. The following figure shows the circuit for a "digital one shot".



Mike Karas