With most projects, it pays to become intimately familiar with the target MCU/CPU architecture and its toolchain. It's appropriate here on an 8052 forum and an 805x target, that if you have memory or speed constraints, hand-rolled assembly is the way to go to address those issues.

In addition to the 8-bit MCU's I work with, I work with the i960 and PowerPC (both 32-bit RISC architectures) in larger embedded systems. It's interesting to compare the mem*** functions with those of the 8051. You would probably be doing yourself a disservice by hand-rolling some straight forward assembly on those platforms. First of all, the library routines for them copy/set bytewise up to a word boundary, then switch to a wordwise (4-byte) copy/set to make better use of the data bus, then shift back down to bytewise to pick up any modulo-wordsize bytes left to copy. For the i960 they even go so far as to use quad-word instructions in the inner loop of the copy/set routines to take advantage of bus bursting capabilities -- 16 bytes at a whack! There are all sorts of other architecture related issues a compiler will consider that an assembly programmer would be hard-pressed to catch. The compilers are usually designed to know how these superscaler architectures' instruction scheduling, multiple execution units, register dependencies, load/store/cache units, etc. work and can take full advantage of them without tiring. For these architectures, and assembly programmer's mind quickly turns to mush. Been there, done that.

Just a bit of multi-platform perspective.