I don't believe that what you want is actually possible.

First of all, there is only one CL register, which is the low clock byte for all PCA modules (in other words: they all share the same clock).

Secondly, you don't get an interrupt when CL reloads to 0 just like that; you would need to configure one of the PCA modules in compare mode for that, but keep in mind that there may be quite a bit of latency, especially if you have configured the PCA clock to f(osc)/4.

Finally, reloading CCAPnH to change the duty-cycle doesn't wait for PCL to roll back to 0, which means that you will get glitches on your outputs and I take it from your posting that you actually want to prevent that.

What do you actually want to make? Is it 3 phase-shifted sine-waves?