I re-read the data sheet again.....It actually says the card remains in read capable mode at all times. Thus I stand corrected on the previous post.

Closer examination reveals that what happens is that it is possible to write the error counter if a bit is still available. This write is possible even without the part in the valid PSC entered state, although a total of only 8 writes are legal. Then the two bytes of the PSC are entered and upon valid PSC input the I/O line will indicate if the inputted value was valid. It would appear that once the error counter has an all bits set state that then an attempt to input a PSC and get the subsequent validation indication on the I/O line is locked out. I now see, as Donald surmised that once the error counter reaches the all bits set that there is no possibility of recovery of the chip to a writable state. If recovery were possible then it would be possible to hack the chip. But clearly the chip is secure (at least from the I/O pins view point. Of course hacking at the chip metalization level with direct to die probing is still an issue).

Michael Karas