non-asserted state would mean that the read strobe, write strobe, and both chip select signals are at their inactive level. And to be complete it may also want to include making the 16-bit data bus lines on the other two ports all look line inputs to the 8052 by setting the port bits all to 1's.

With the interface you have setup there are one of four asserted states possible at any given time. They are:

1) CS0 active with IOW active (data ports must be set to output data)
2) CS0 active with IOR active (data ports must be inputs)
3) CS1 active with IOW active (data ports must be set to output data)
4) CS1 active with IOR active (data ports must be inputs)

Good luck.....seems like an interesting project.

Michael Karas