| ??? 03/27/03 20:11 Read: times |
#42388 - RE: NoTouch... again Responding to: ???'s previous message |
You are obviously confoosing the 'funny pin level' (hardware) start of ISP with the NoTouch approach (software).
Yes. It makes sense now! The novelty of your NoTouch approach is to avoid meeting those hardware conditions. The danger of using the hardware method + manual reset is the EMI generated from those actions. Using the watchdog is a better method because it reduces EMI? The only drawback is that the chip needs to be programmed with this code at least once. This is no problem for someone with a parallel programmer. For me, I guess I will require some jumpers to bootstrap it into that condition. A jumper on PSEN should be enough (P2.7, 2.6 would always be pulled high on a reset, ALE always disconnected). Hardware programming method -> ground. Otherwise, no connection. I think it will be pulled high internally (although I can't confirm that from the datasheet). Ah dunno, what is DTR connected to on the RD2 DTR will go to my reset chip (ADM708), which generates the reset signal. This would not be needed for your NoTouch method, only for the first time programming. Maybe I should put this on a jumper as well, only to be used when the hardware programming method is used. What I was thinking was to put a jumper on P3.7 (an available pin), to pull it to ground (is it safe to go directly, or should I use a 2k resistor?) if I want to go into programming mode. This pin would be continually checked in my main while loop. So now I'm wondering about your assembly code that you have provided in the NoTouch document. GoToBoot: mov AUXR1,#020h ;enable boot mov r0,#20 ;oscillator freq = 20Mhz mov r1,#6h ;program status byte mov dptr,#0 ;specify status byte mov a,#0ffh ;nonzero required call 0fff0h jmp $ ;wait for watchdog to reset end Line 1: I understand, enable the boot rom shadowing. Line 2 + 3: r0 and r1 need to be set to configure the crystal frequency and the status byte, but aren't these lost when the watchdog resets the chip? Line 4 + 5: Clear the DPTR, put 0FFh in the accumulator. Why? Line 6: You've lost me. Put fff0h in the PC and go to that location? What if there is code in that area? Or should my code have something there. Line 7: Jump to where??? Shouldn't the watchdog timer be enabled at some point? Also, where is the boot vector located? I couldn't find it in the datasheet. I don't want to change it, I'm just curious. :) Thanks Erik, I appreciate all your help. |
| Topic | Author | Date |
| NoTouch... again | 01/01/70 00:00 | |
| RE: NoTouch... again | 01/01/70 00:00 | |
| RE: NoTouch... again | 01/01/70 00:00 | |
| RE: NoTouch... again | 01/01/70 00:00 | |
| RE: NoTouch... again | 01/01/70 00:00 | |
| RE: NoTouch... again | 01/01/70 00:00 | |
| RE: NoTouch... again | 01/01/70 00:00 | |
RE: NoTouch... again | 01/01/70 00:00 |



