Man oh man this is hard. Maybe it is because the data sheets are written in TI-ese and the reader is only familiar with TOSHIBA-ese.

In any case....in an nutshell

'HC165. - 8-Bit Parallel In/Serial Out Shift Register

One would use this part with a microcontroller to increase the input pin count available to the processor. Some logic, which is most likely a port pin, will pulse the /PE pin low which captures the data on the D0->D7 pins into a set of 8 flipflops inside the part. Then the /PE is raised high and the microcontroller can assert /CE low and sequence a series of shift pulses on the CP pin (most likely via an output pin). This makes the data in the flipflops appear on the Q7 output in a sequential manner. The Q7 pin can be connected to an input on the microcontroller so that the processor can gather in the data bits one-by-one in between each CP pulse generated. One chip can give you the ability to read 8 input states to the processor in place of the 4 pins it takes to manage the /PL, /CE, CP, and Q7 pins. It is possible to connect multiples of these chips up in series to gain additional input capability in groups of 8 bits per chip. All of the chips would be wired to the same /PL, /CE, and CP outputs from the microcontroller while the Q7 from the first chip wires to the DS pin of the next chip in sequence whilest the Q7 of the last chip connects to the input pin on the processor. These chips essentially permit the processor to read 8, 16, 24, .... n*8 input signals in a serial manner. A data sheet for this part can be seen at:

TI 74HC165 Data Sheet


'HC4094. - 8-Bit Shift and Store Bus Register, Three-State

One would use this part with a microcontroller to increase the output pin count available to the processor. Some logic, which is most likely a port pin, connects to the CP pin on the part. Another output pin connects to the DATA pin. The microcontroller will then place a series of data bit values in turn on this DATA pin and then for each will pulse the CP pin. This shifts the data out to the part where it is captured in the shift register portion of the IC. After the shifting is complete the STR pin can be pulsed to move the data from the shift register portion to the holding register portion of the chip. The outputs of the holding register then drive the Q0->Q8 outputs of the chip provided the OE pin is driven to a HI level. This holding register concept is useful because it permits all the outputs to be updated at once. If instead the outputs were connected to the shift register the outputs would all be changing each time the processor toggled the CP line. One chip can give you the ability to write 8 output states from the processor in place of the 3 or 4 pins it takes to manage the DATA, CP, STR and possibly the OE pins. (It is possible that the OE pin is simply pulled high if the three-state feature is not used). It is also possible to connect multiples of these chips up in series to gain additional output capability in groups of 8 bits per chip. All of the chips would be wired to the same CP, STR, and OE pins from the microcontroller while the DATA from the first chip wires to the output pin from the microcontroller. The QS1 pin then wires to the DATA pin of the next chip in sequence whilest the QS1 pin of the last chip is normally not connected. These chips essentially permit the processor to write 8, 16, 24, .... n*8 output signals in a serial manner. A data sheet for this part can be seen at:

TI 74HC4094 Data Sheet

Hope you can read TI-ese because that is the flavor of these referenced data sheets.

Michael Karas