| ??? 05/13/03 13:53 Read: times |
#45360 - Newbie on the \ |
Hi,
I am a newbie to this forum. I just bought a PJRC 8051 board and have a question about the "Negative Logic" concept. Mainly to ensure that I am understanding this correctly and won't "run into trouble" later on. In the "Bible" on page 3-7, I found this paragraph: "Ports 1,2, and 3 have internal puUups. Port O has open drain outputs. Each I/O line can be independently used as an input or an output. (Ports O and 2 may not be used as general purpose I/O when being used as the ADDR/DATA BUS). To be used as an input, the port bit latch must contain a 1, which turns off the output driver FBT. Then, for Ports 1, 2, and 3, the pin is pulled high by the internal pullup, but can be pulled low by an external source. Port O differs in not having innternal pullups. The pullup FET in the PO output driver (see Figure 4) is used only when the Port is emitting 1s during external memory access, otherwise the pullup FET is off. Conaequently, PO lines that are being used as output port lines are open drain. Writing a 1 to the bit latch leaves both output FETs off, so the pin floats. In that condition it can be used a high-impedance input. Because Ports 1, 2, and 3 have fixed internal pullups they are sometimes called “quasi-bidirectional” ports. When configured as inputs they pull high and will source current (IIL, in the data sheets) when externally pulled low. Port O, on the other hand, is considered “true” bidirectional, because when configured as an input it floats. All the port latches in the 8051 have 1s written to them by the reset function. If a O is subsequently written to a port latch, it can be reconfigured as an input by writing a 1 to it." So for 1, 2, and 3, writing a 1 to the latch causes not Q to be low, turning off FET and presenting a high to external source? So external souce must be able to sink IIL referenced current to ground to pull port low and so "0 = on state" because if port is 0 to external souce, port cannot be pulled high by external souce due to FET grounding? External source shouldn't source port high but rather should float pin (very high impedance) to avoid excessive current? Please correct my understanding if I am in error. I have read posts and want to be sure that my limited knowledge is being applied in the correct manner. Thanks to all for this great information source. Ted |
| Topic | Author | Date |
| Newbie on the \ | 01/01/70 00:00 | |
| RE: Newbie on the \ | 01/01/70 00:00 | |
RE: Newbie on the \ | 01/01/70 00:00 |



