I would like to share a couple of app notes to respond to Sanjeev's buffer question. He asked a hypothetical question about interfacing logic chips that use separate power supplies.

The following app notes discuss several aspects of this problem:

Zarlink's Understanding and Eliminating Latch-up in CMOS Applications

Maxim-IC's Multiple Voltage Systems Need Supply-Voltage Sequencing. (OK, this one doesn't apply to this particular question.. It is still interesting though.)

I look forward to the feedback from experienced designers. I wonder if following the recommendations to a T will result in an unnecessarily over-engineering solution.

- Lee