Sounds to me like some aspect of your circuit is causing an I/O pin on some IC part to go way higher then VCC or way lower than GND in voltage when the telephone line is attached to your prototype. One or both of these conditions can induce CMOS latchup inside an IC. And it is possible that this latchup can persist even after you remove both the high/low voltage condition that induced the latchup and the normal power from the circuit board. Several times in my career I have even seen latch up conditions that persisted in ICs until they were removed from the circuit, strange as that may seem.

I can relate one or more of these experiences if you desire. But the first thing I would check is if you are having an unintended latch inducing condition on your board. If you find that then you are quicker to solving your problem than me telling a long story. If you cant seem to find the condition come back and I can tell you some things to look for that are not immediately obvious. For instance....sometimes a latch-up inducing condition can happen because a capacitor pushes the IC pin above VCC or below GND when a signal on the other side of the capacitor experiences a transient such as an edge transition or pulse.

Michael Karas