There was someone who was asking about interfacing sdram simms to the 8052.
As promised I had a look at it and I have taken a xilinx reference design for a 125Mhz sdram interface and modified it to move it away from the need to use high speed buffers implemented in the virtex FPGAs and made changes to the buffering so that it can now be used in the much cheaper xc9500xl series CPLD.It is capable of supporting 66Mhz sdram simms in upto 8 byte
read/write bursts,has a memory mapped 8052 interface and I have hopefully solved the clock skew problems which required the use of DDls in the VIRTEX design.I have performed functional simulation with a micron mt48lc1m16a1 and it seems ok.
if anyone wants to have a play and see if they can use it or wants to try and fit it to some other vendors part drop me a line.