| ??? 07/23/03 15:54 Read: times |
#51216 - RE: cygnal development board Responding to: ???'s previous message |
While I agree with all the above, I want to post a warning for Cygnal users.
You MUST decide ALL things related to which I/O you want enabled. When you add or subtract one, the I/O already enabled moves to other pins. This does not in any way reflect badly on the chip, it just forces you to know what you want to do before you start, which should be the case anyhow. I happened to get a design spec change before a PCB with a Cygnal chip was made, had I gotten it later the PCB would have had to be remade. In this particular case I would not have had to redo the PCB had I used a 'regular' '51 and a CPLD as I usually do, thus the warning. Erik |
| Topic | Author | Date |
| cygnal development board | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
| RE: Cygnal warning - Erik | 01/01/70 00:00 | |
| RE: cygnal development board | 01/01/70 00:00 | |
RE: Keil uv2 and Cygnal IDE | 01/01/70 00:00 |



