Intel knew that when they give the guys power to alter the priority levels, confusion is a natural outcome!!

So what they did was to have an internal polling sequence of interrupt sources when you set more than 1 interrupt to high priority. This sequence kind of acts like the ultimate arbitrator.

So the internal sequence is ( Highest priority to Low priority ):

INT0
TF0
INT1
TF1
RI+TI

Assuming you dont mess around with the priority levels then the above is the sequence. And assume you set all of them to High priority - once again the sequence is the same !

Raghu