Actually, using the processor to do the phase control is difficult but possible with a 16 MHz processor. The 16 channels are received into a 16-byte buffer, then a background task (no hurry here) arranges them into a list of byte events for the triacs.

Let's simplify to the 8-channel case; a timer interrupt occurs every (8.33/128) milliseconds (65 uS) and sends one byte to the output port, increments its counter, and returns. (Sorry, this only does 128 different levels). The 16-channel case requires a bigger table and a little bit more time, and might be limited to 64 levels.

The key to making this work is that you need to leave some time for the background task to create the table.

If you want to spend more time in background processing and less time in interrupts, you can create a schedule where the timer is loaded with the time to the first triac event, then the second, and so on. This is much more complex but only requires one timer interrupt per active output. Serial reception becomes extremely reliable which is a big plus.