The edge triggered interrupt will set the interrupt flag when there is a negative transition on the INTx pin. This means that subsequently the processor will execute an interrupt if the INTx pin interrupt enable flag is set and if the EA global interrupt enable flag is set. After the negative edge the interrupt will occur irregardless if the input stays low or goes back high. ANother interrupt will not occur until the interrupt flag is cleared and then when the INTx pin makes a next high to low transition. Note that the interrupt flag in this edge triggered mode is automatically cleared by the 8052 hardware at time the processor vectors to the interrupt service routine.

In the case of a level triggered interrupt the interrupt flag is set whenever the INTx pin is at a low level. If the INTx pin was initially high the interrupt would be armed at the time the pin went low and would stay armed as long as the pin is low. Subsequently the processor will execute an interrupt if the INTx pin interrupt enable flag is set and if the EA global interrupt enable flag is set. In the level mode the interrupt flag is not automatically cleared and it is the responsibility of the system designer and software coder to work out a scheme to get the interrupt flag cleared. This is often done via some I/O activity to the interrupting device that is driving the INTx pin. If the INTx pin is left low and the corresponding external interrupt flag is still set and the global EA flag is still set then the processor will immediately queue another interrupt and will do so until the interrupt level is taken high or one of the enabling flags is cleared.

Michael Karas