hi,
In my code the write_spi_byte adresses dph & dpl "separately", not dptr. Could this be a problem?
Exactly! Many modern C51s have some DPTRs but only one DPTR is *visible* inside SFR space at one time. Opposite it, 8252 has both DPTRs presented in SFRs at different addresses. So users sometimes are confuced and make a error when use DPH/DPL. Atmel has described the problem here: http://www.atmel.com/dyn/resou...OC1018.PDF at chapter "Dual Data Pointers". The common mistake is that, for example, after switching DPTR1 user reads/writes DPH0/DPL0 but REALLY he does it with DPH1/DPL1 because datasheet says:
IMPORTANT: The state of DPS affects ALL accesses to the data pointer SFRs (82H, 83H, 84H, 85H). Any machine instruction whose operand is one of the data pointer SFR may produce unexpected results, as shown below:

DP0L DATA 82h ; data pointer 0
DP0H DATA 83h ;
DP1L DATA 84h ; data pointer 1
DP1H DATA 85h ;

orl  WMCON,#DPS  ; set DPS
push DP0L        ; PUSHES DP1L!!!
mov  83h,a       ; COPIES ACCUMULATOR TO 85H!!!
xrl  WMCON,#DPS  ; clear DPS
push DP1H        ; PUSHES DP0H!!!
mov  84h,a       ; COPIES ACCUMULATOR TO 82H!!

Do not ask me WHY mov 83h,a copies ACC to location 0x85 - I do not work in Atmel :) Probably, you have the same problem in your code.

As about
Could you point me out the difference between "setb" operation at WMCON and direct XRL (toggling the DPS bit). It SHOULD result in same result?
SETB is not possible for WMCON - it is not bit-addressable. If you mean load its value into ACC, modify it and write back:
well, it takes 6 bytes of code and 3*12 OSC cycles. XRL/ANL/ORL of direct address (if you need toggle/clear/set corresponded bit[s]) takes 3 bytes of code and 1*24 cycles. Moreover, it keeps ACC from usage what is useful sometimes. So, at main: it faster, it saves code space and register usage. Just note, that you need to use correct mask value: for XRL/ORL a mask should have the corresponded bit set (1) and all others clean (0); for ANL is should be vice-versa.

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